In a conventional vertical power Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET), two p-body regions are formed in an n-type epitaxy region. The vertical power MOSFET are such named since its source and drain regions are overlapped. A portion of the epitaxy region between the two p-body regions is lightly doped to form an n-type doped region, which is sometimes known as an N-type Junction Field Effect Transistor (n-JFET) region. The p-body regions and the n-JFET region are under a gate dielectric and a gate electrode. When the gate is applied with a positive voltage, inversion regions of electrons are formed in the p-body regions. The inversion regions act as the channel regions that connect the source region of the vertical power MOSFET to the n-JFET region, which is further connected to the drain region of the power MOSFET through the n-type epitaxy region. Accordingly, a source-to-drain current is conducted from the source region to the channels in the p-body regions, the n-JFET region, the epitaxy region, and then to the drain region.
The n-JFET region is underlying the gate electrode, with the gate dielectric layer disposed between the n-JFET region and the gate electrode. There is a large overlap area between the gate electrode and the n-JFET region. As a result, there is a significant gate-to-drain capacitance, which adversely affects the performance, including the speed, of the vertical MOSFET. Furthermore, the n-JFET region is lightly doped since is it a part of the n-type epitaxy region. The resistance of the n-JFET region is thus high, which adversely affects the drive current of the vertical power MOSFET.